Senior Front End Design Engineer (Microarchitecture)

Cerebras Systems

$250K — $300K *
Telecommunications & Hardware
8 - 10 years of experience
Job Overview by Ladders

Qualifications

  • Master's in Computer Science, Electrical Engineering, or equivalent
  • 8+ years of experience in complex RTL designs
  • Expertise in Front End Chip and third-party IP integration
  • Experience in networking, high-performance computing, or machine learning
  • Proven track record of silicon project success
  • Knowledge of PCIe, CPU interfaces, and Serdes technology
  • Working knowledge of scripting tools like Python and TCL

Responsibilities

  • Drive chip design aspects including specification, micro-architecture, and RTL development
  • Collaborate with physical design team for design closure to meet performance goals
  • Partner with verification and DFT teams for optimal functional and test coverage
  • Engage with software and system teams to enhance performance and features
  • Debug silicon-level functional, timing, and power issues during bring up

Benefits

  • Hybrid work environment
  • Access to advanced semiconductor technology
  • Opportunity to collaborate with a world-class team
  • Involvement in groundbreaking projects within the high-performance computing space
Full Job Description
About The Role

As a senior front-end design engineer, you will be a key part of the world-class team designing and developing the next generations of the Cerebras Wafer Scale Engine (WSE). This role requires deep expertise in RTL design and integration, with a strong focus on delivering high-performance, power-efficient, and scalable solutions. You will collaborate closely with the design verification, physical design, software and system teams to bring innovative semiconductor architectures from concept to production, addressing the unique challenges of building WSE systems.

Responsibilities
  • Drive all aspects of chip design, including Functional Specification, Micro-architecture, RTL development, Synthesis.
  • Work closely with PD team members for design closure to meet PPA goals.
  • Work closely with Design verification and DFT teams for achieving the best functional and test coverage.
  • Work with software and system teams to understand opportunities to deliver optimal performance and feature set for the product.
  • Debug silicon-level functional, timing, and power issues during bring up.

Requirements
  • Master's degree in Computer Science, Electrical Engineering, or equivalent.
  • Can work in a hybrid work environment.
  • 8+ years of experience in delivering complex, high performance high quality RTL designs.
  • Experience with Front End Chip integration and third-party IP integration.
  • Demonstrated experience in networking, high-performance computing, machine learning or related fields.
  • Proven track record of multiple silicon success.
  • Experience collaborating with external vendors.
  • Networking stack experience including TCP/IP, RDMA and Ethernet.
  • Knowledge of PCIe, CPU interfaces and Serdes technology.
  • Working knowledge of scripting tools : Python, TCL.

Assets
  • Experience with FPGA development toolchain, including Place and Route, Floor planning and Timing Analysis is a plus.
  • Experience managing external ASIC vendor through product development cycle.


Location: Sunnyvale, CA

The base salary range for this position is $250,000 to $300,000 annually. Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.

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