Job Area:Engineering Group, Engineering Group > ASICS Engineering
General Summary:The successful candidate will join the Display IP Design team in developing leading edge display solutions in Qualcomm SoC's. We are looking for individuals that possess internal drive and keen desire to learn on the job. You will work within a multi-disciplinary, multi-site team of architects, designers and verification engineers and will be responsible for the IP design development and integration within the display sub-system.
New PositionPrincipal Duties:- Develop of Micro-Architecture and specification based on high level design requirements
- Develop RTL design that meets required performance and is optimized for Area and Power
- Integrate pre-verified sub-IPs to build up larger functionality
- Flow bring up and report analysis for Linting, RTL Synthesis, CLP, CDC
- Work closely with verification team to define testplan, debug regression, analyze coverage reports
- Develop SVA assertions for white box verification for formal verification
- Effective communication across teams, multitasking and well-planned execution of the tasks.
Preferred Qualifications:- Prior experience delivering Verilog and System Verilog RTL
- Detail oriented with strong analytical and debugging skills
- Strong communication (written and verbal), collaboration, and specification skills
- Practiced design knowledge working with some of the following concepts:
- Clock domain crossing and reset architecture
- Machine Learning HW development
- FIFOs implementation
- Bus implementation/verification techniques
- Memory selection and control
- High speed and low power design optimization
- Bus interface protocols (AHB, AXI)
- Experience with some of the following
- Simulation and code coverage tools (VCS, Verdi, Modeltech/Questa, or Xcelium)
- Design rule and CDC checking (SVA assertions, Spyglass, 0-in, etc.)
- Scripting languages (PERL, Python, TCL, C, etc.)
- Power Intent and Analysis: UPF, CLP, PTPX, PowerPro
- Synthesis: DCG/NXT, FC
- Static Timing: Primetime
- Formal Verification: Conformal, Formality
Minimum Qualifications:- Legally permitted to work on-site in Canada
- 2+ years of ASIC design experience.
Minimum Qualifications:• Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field.
Pay range and Other Compensation & Benefits:$104,900.00 - $154,900.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer.
If you would like more information about this role, please contact Qualcomm Careers.
