Principal SerDes Design Engineer

Celero Communications, Inc.

• $200K — $300K *
US-AnywhereRemote in Irvine, CA
Telecommunications & Hardware
8 - 10 years of experience
Job Overview by Ladders

Qualifications

  • Master's degree or PhD in Electrical Engineering or related field
  • 10+ years of experience in SerDes design
  • Proven track record of high-speed SerDes from tape-out to production
  • Extensive knowledge of advanced node technologies (16nm to 2nm)
  • Experience in cross-functional team collaboration
  • Strong communication and documentation capabilities

Responsibilities

  • Define architecture and specifications for next-gen SerDes
  • Oversee system-level modeling and analysis using behavioral tools
  • Design high-performance analog/mixed-signal circuits
  • Develop critical components like RX/TX equalization and PLLs
  • Implement digitally-assisted analog circuits for optimization
  • Manage physical layout designs to reduce parasitics and enhance performance
  • Lead lab validation, debugging, and performance correlation with simulations

Benefits

  • Dynamic work environment focused on innovative technology
  • Opportunity to work on cutting-edge AI-related projects
  • Access to advanced lab facilities for testing and validation
  • Collaboration with cross-functional teams on impactful designs
  • Professional growth through challenging and high-tech projects
Full Job Description
Principal SerDes Design Engineer

About the job
We are looking for a SerDes Lead Designer, who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology to power next generation AI. Candidate will have the opportunity to architect and design SerDes for next generation transceivers.

What You Will Do
• Define architecture, specifications, and circuit topologies for next-generation SerDes
• Overview development of system-level modelling, with behavioral models (e.g., MATLAB, SystemVerilog, Verilog-A) to analyze link budgets, equalization strategies and jitter budgeting
• Design high-performance analog/mixed-signal circuits in advanced node technologies
• Develop and overview the design of critical blocks including RX/TX equalization (CTLE, DFE), High-speed PLLs, Phase interpolators, DLLs, TDCs
• Implement digitally assisted analog circuits, background calibration, and adaptive loops to improve Power, Performance, Area
• Oversee physical layout to minimize parasitics, device stress, electromigration and process variation impacts
• Overview of the analysis of Signal Integrity and Power Integrity to achieve system-defined targets
• Lead lab validation, debugging and characterization of SerDes IPs within our state-of-the-art lab
• Correlate silicon measurements with simulated data, and lead performance optimization in the system environment

What You Will Bring
• Master's degree and/or PhD in Electrical Engineering or related fields with 10+ years of relevant experience in SerDes design
• Proven record of taking high-speed SerDes design to tape-out and volume production
• Experience in lab bring-up, characterization, and debugging designs that reach out production
• Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)
• Prior experience in cross-functional interaction to deliver IP and ensuring seamless integration in SOCs
• Strong communication and documentation skills

Annual Base Salary Range: $200,000 - $300,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)

Javier Leon
Talent Acquisition

[email protected]
www.celero.inc

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