Principal SerDes Design Engineer

Celero Communications, Inc.

$200K — $300K *
US-AnywhereRemote in San Jose, CA
Telecommunications & Hardware
8 - 10 years of experience
Job Overview by Ladders

Qualifications

  • Master's degree and/or PhD in Electrical Engineering or related fields
  • 10+ years of experience in SerDes design
  • Proven success in high-speed SerDes design to tape-out and volume production
  • Experience with advanced node technologies (down to 2nm)
  • Strong communication and documentation skills

Responsibilities

  • Define architecture, specifications, and circuit topologies for SerDes
  • Develop system-level modeling with tools like MATLAB and SystemVerilog
  • Design high-performance analog/mixed-signal circuits
  • Oversee the design of RX/TX equalization and critical components
  • Implement digitally assisted analog circuits for optimization
  • Minimize parasitics and process variation in physical layout
  • Lead lab validation, debugging, and characterization of SerDes IPs

Benefits

  • Opportunity to work on disruptive technology for next-gen AI
  • Engage in cutting-edge projects with state-of-the-art labs
  • Collaborative environment with cross-functional teams
  • Focus on innovative solutions and advanced design processes
  • Career advancement potential in a rapidly evolving field
Full Job Description
Principal SerDes Design Engineer

About the job
We are looking for a SerDes Lead Designer, who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology to power next generation AI. Candidate will have the opportunity to architect and design SerDes for next generation transceivers.

What You Will Do
• Define architecture, specifications, and circuit topologies for next-generation SerDes
• Overview development of system-level modelling, with behavioral models (e.g., MATLAB, SystemVerilog, Verilog-A) to analyze link budgets, equalization strategies and jitter budgeting
• Design high-performance analog/mixed-signal circuits in advanced node technologies
• Develop and overview the design of critical blocks including RX/TX equalization (CTLE, DFE), High-speed PLLs, Phase interpolators, DLLs, TDCs
• Implement digitally assisted analog circuits, background calibration, and adaptive loops to improve Power, Performance, Area
• Oversee physical layout to minimize parasitics, device stress, electromigration and process variation impacts
• Overview of the analysis of Signal Integrity and Power Integrity to achieve system-defined targets
• Lead lab validation, debugging and characterization of SerDes IPs within our state-of-the-art lab
• Correlate silicon measurements with simulated data, and lead performance optimization in the system environment

What You Will Bring
• Master's degree and/or PhD in Electrical Engineering or related fields with 10+ years of relevant experience in SerDes design
• Proven record of taking high-speed SerDes design to tape-out and volume production
• Experience in lab bring-up, characterization, and debugging designs that reach out production
• Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)
• Prior experience in cross-functional interaction to deliver IP and ensuring seamless integration in SOCs
• Strong communication and documentation skills

Annual Base Salary Range: $200,000 - $300,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)

Javier Leon
Talent Acquisition

[email protected]
www.celero.inc

Similar Jobs

More Jobs at Celero Communications, Inc.

More Telecommunications & Hardware Jobs

Find similar Principal SerDes Design Engineer jobs: