The OpportunityWe are seeking a highly experienced and visionary
Principal Mixed-Signal Design Verification (MSDV) Engineer & Team Lead to join our team. In this critical leadership role, you will champion the verification of our next-generation Power ICs (including advanced Motor Drivers, PMICs, and Gate Drivers). You will lead a talented team of verification engineers, driving technical excellence from initial chip architecture down to final tape-out sign-off.
What You Will Do In this role, you will be responsible for the end-to-end verification strategy, methodology, and team execution within our Power IC business line:
- Lead, develop, and mentor the Mixed Signal Verification Team
- Define and implement state-of-the-art mixed-signal verification methodologies-including pioneering the exploration and integration of AI-driven automation tools-to streamline the global verification flow.
- Own all aspects of design verification (MSDV) for complex mixed-signal ICs, executing the complete cycle from initial test planning to the final, tape-out-ready Verification Report.
- Partner closely with Systems and Design Engineering teams to contribute to top-down chip architecture definitions and pre-design feasibility studies.
- Architect and construct robust, scalable, object-oriented SystemVerilog/UVM testbenches (including Scoreboards, Sequencers, Drivers, and Monitors) and class objects to be easily reusable by the wider global team.
- Requirements Traceability & Safety Compliance:
- Translate system requirements managed in Jama into automated verification tests
- Verify and document ISO 26262 Hardware Safety Requirements (ASIL compliance)
- Develop assertions (SVA) to enforce strict analog and digital boundaries.
- Train and guide engineers to interpret analog schematics, generate accurate behavioral models (amplifiers, comparators, gate drivers, oscillators, LDOs, ADCs/DACs), and generate top-level netlists for seamless simulation within Cadence Mixed-Signal environments
- Establish automated regression flows and track pre-silicon design and verification issues utilizing GitLab as our primary engineering interface
What You Will Bring - Bachelor's or Master's degree in Electrical Engineering, Microelectronics, or a highly related technical field.
- 8+ years of hands-on experience in Mixed-Signal Design Verification (MSDV). Strong background in power-related topologies (Motor Drivers, PMICs, Gate Drivers) is highly preferred.
- Proven track record of developing comprehensive full-chip verification plans, managing execution schedules, tracking regression metrics, and driving functional and code coverage closure for tape-out sign-off
- Expertise in SystemVerilog, SVA (Assertions), and UVM methodologies.
- Proficiency in scripting languages (e.g., Python, Bash, Perl) to drive automation and efficiency.
- Strong familiarity with Cadence mixed-signal simulation environments.
- Deep understanding of analog and mixed-signal blocks to guide the team in writing high-fidelity behavioral models (PLLs, Charge Pumps, Bandgaps, etc.).
- A passion for coaching and developing junior-to-mid level engineers, helping them transition into independent, highly technical contributors.
Eligible applicants must reside in a state where Allegro currently has an office location: This includes New Hampshire, Massachusetts, Texas, and Michigan. Certain positions (such as field sales roles) may be exempt from this requirement.
