Job Details:Job Description:We are seeking a Principal Collateral Device Engineer to join our team within MDCE. This role requires regular onsite presence to fulfill essential job responsibilities and will creates next generation device and interconnect technology by ensuring the process device performance for developing processes is world class, using deep understanding of device physics.
Key Responsibilities:
- Demonstrated expertise in leading cross functional group in defining derivative architectures including Design rules, transistors and interconnects. Expertise in CMOS semiconductor device physics and test chip design for advanced transistor device architecture.
- Experience in scribe line layout design and process monitoring structure development.
- Proficiency in design rule development, validation, and waiver management processes.
- Strong understanding of DTCO skills Including understanding of SRAM, Standard cells and be the key interface and bridge between Process Integration , Yield, Device and Design.
- Strong skills in data analysis, scripting, and statistical techniques for test chip data interpretation.
- Excellent technical problem-solving skills with ability to balance design rule compliance with customer flexibility needs.
- Ability to work collaboratively in globally diverse, cross-disciplinary teams to develop innovative device collateral solutions.
- Demonstrated experience with design of experiment (DOE) principles applied to device collateral optimization.
- Proven track record of delivering device collateral solutions in a fast-paced manufacturing environment.
- Desire to learn, lead, and influence cross-functional teams in collateral development and design rule optimization.
Qualifications:You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
- Master's degree in Electrical Engineering, Physics, or related field
- 15+ years of experience in CMOS device engineering with focus on test chip design and device collateral development
Preferred Qualifications:
- Ph.D. degree in Electrical Engineering, Physics, or related field
- 15+ years of experience in CMOS device engineering and collateral development
- Hands-on experience in advanced node test chip design and scribe line optimization for 3nm-16nm FinFETs and sub 3nm GAA FETs
- Experience with design rule checker (DRC) development and physical verification flows
- Experience in High-Volume Manufacturing environment with focus on yield monitoring and process control structures
- Knowledge of statistical process control (SPC) and advanced data analytics for device collateral optimization
- Knowledge of mask generation including Boolean/OPC .
Job Type:Experienced Hire
Shift:Shift 1 (United States of America)
Primary Location:US, California, Santa Clara
Additional Locations:US, Arizona, Phoenix, US, Oregon, Hillsboro
Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
