Modelling Lead (SystemC / Virtual-Platform Architect)

Lumilens

$130K — $180K *
US-AnywhereRemote in San Jose, CA
Aerospace & Defense
8 - 10 years of experience
Job Overview by Ladders

Qualifications

  • 8+ years in architecture/performance modeling or virtual-platform development for complex SoCs.
  • Strong proficiency in SystemC and TLM-2.0; solid skills in modern C++.
  • Experience in building or leading a virtual platform that real firmware ran on pre-silicon.
  • Proficient in integrating third-party ISS into a SystemC/TLM platform; adept at modeling buses and peripherals.
  • Deep understanding of architecture/performance modeling - ability to determine what to abstract versus model accurately.
  • Familiarity spanning hardware micro-architecture and embedded software.

Responsibilities

  • Develop a SystemC/TLM-2.0 virtual platform that supports firmware before RTL is available.
  • Conduct architecture and performance models, including architectural trade studies and throughput analysis.
  • Create golden reference models to serve as scoreboards for the design verification team.
  • Design behavioral models for analog and control circuits.
  • Collaborate with front-end architects and firmware leads to ensure alignment across models, RTL, and firmware.

Benefits

  • Comprehensive benefits package including health, dental, and vision.
  • Professional development opportunities and certification support.
  • Access to cutting-edge technology and cloud platforms.
  • Collaborative work environment with cross-functional teams.
Full Job Description
About the role. You will build the executable model of the chip before silicon exists. Your architecture models will settle the decisions that are expensive to change late, including datapath latency, throughput, buffer sizing, and control-loop tuning. Your reference models will become the golden checkers the verification team scores against, and the platform will run real firmware months ahead of RTL. This is a founding, critical-path role: the virtual platform is what unblocks the firmware and architecture work in parallel with design.

What You'll Own
  • A SystemC/TLM-2.0 virtual platform - MCU (ISS-backed) + peripherals + memory map + a UCIe transactor + host stub - that firmware runs on pre-RTL.
  • Architecture/performance models: architectural trade studies, end-to-end datapath throughput and latency, FIFO/buffer sizing, design-space/configuration exploration.
  • Golden reference models handed to DV as scoreboards.
  • Behavioral models of the analog and control circuits.
  • Partner with the FE architect and firmware lead to keep model, RTL, and firmware views coherent.

Required
  • 8+ years in architecture/performance modelling or virtual-platform development for complex SoCs.
  • Strong SystemC and TLM-2.0; solid modern C++.
  • Built or led a virtual platform / ESL model that real firmware ran on for pre-silicon bring-up.
  • Integrating a third-party ISS (e.g., Arm or RISC-V) into a SystemC/TLM platform; modelling buses, memory maps, and peripherals.
  • Architecture/performance modelling judgment - knowing what to abstract versus model faithfully.
  • Comfortable spanning hardware micro-architecture and embedded software.

Preferred
  • Familiarity with High-speed serial links and die-to-die / chiplet interconnects, and link-layer concepts such as FEC and equalization (e.g. PCIe, UALink, Ethernet or memory-semantic interconnects like CXL).
  • Experience feeding golden models into a UVM/DV verification flow.
  • Modelling for mixed-signal or optical/SerDes systems, including control-loop / plant modelling.
  • High-throughput datapath modelling.

What We Offer
  • Competitive salary commensurate with experience
  • Comprehensive benefits package including health, dental, and vision
  • Professional development opportunities and certification support
  • Access to cutting-edge technology and cloud platforms
  • Collaborative work environment with cross-functional teams

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