Job Requirements The achievers and courageous challenge-crushers we seek, have the following characteristics and skills:
We are looking for a Senior Physical Design Engineer with 8-14 years of experience to lead and execute RTL to GDSII implementation for low power SoCs on advanced nodes. This role demands deep expertise in Synopsys Fusion Compiler, strong scripting and automation, and a proven track record of achieving best-in-class PPA.
What You will Do:- Drive physical design flow: synthesis, floorplanning, placement, CTS, routing, timing closure.
- Deliver low power designs using advanced UPF methodologies on 5nm/3nm nodes.
- Resolve SoC/SS integration challenges including SDC constraints and UPF promotion/pushdown.
- Develop and maintain automation flows using Tcl, Python, and Shell.
- Collaborate with cross-functional teams for design closure and signoff.
- Mentor and lead junior team members.
- Innovate and contribute to flow/methodology improvements.
What You Will Bring:- B.Tech/M.Tech in ECE, EE, or VLSI.
- 8-14 years hands-on physical design experience.
- Expert in Fusion Compiler, low power design, and PPA optimization.
- Strong scripting skills (Tcl/Python/Shell).
Pay Range: $65.00-$75.00/hr.
Compensation decisions are made based on factors including experience, skills, education, and other job-related factors, in accordance with our internal pay structure. We also offer a comprehensive benefits package, including health insurance, paid time off, and retirement plan.
Work Requirements:This role is considered an on-site position located in Santa Clara, CA
• You must be able to commute to and from the location with your own transportation arrangements to meet the required working hours.
• Shop floor environment, which may include but not limited to extensive walking, and ability to lift up to 40 lbs.
Option 3 (Remote): This position is classified as Remote within the United States.
Benefits Full-time (Temporary)• 401(k)
• Dental insurance
• Health insurance
• Vision insurance
