Advanced Micro Devices, Inc

Fullchip Floorplan Design Engineer

Advanced Micro Devices, Inc • $100K — $130K *
Markham, ON L3R 0G6In-Person
Consumer Technology
Less than 5 years of experience
Today
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Job Overview by Ladders

Qualifications

  • Bachelor's or master's degree in electrical engineering, computer engineering, or related field preferred
  • 5-7 years of experience in physical design and full-chip floorplanning
  • Hands-on experience with Fusion Compiler or similar tools (e.g., Innovus)
  • Proficiency in scripting languages (Tcl, Perl, Python, Shell) for automation
  • Strong understanding of SoC architecture and physical design flows
  • Demonstrated success in chip tapeouts and collaboration with diverse technical teams

Responsibilities

  • Own full-chip floorplanning including partitioning, macro placement, and integration
  • Translate RTL into a detailed full-chip floorplan, defining chip structure and block definition
  • Plan pins, feedthroughs, and bus topology for effective data handling
  • Define and implement a repeater strategy for optimal timing and signal integrity
  • Optimize the floorplan for timing, power, and area (PPA)
  • Conduct feasibility and tradeoff analysis for decision-making in floorplanning
  • Collaborate closely with RTL, architecture, DFT/DFX, and PD teams to ensure seamless execution
  • Develop automation scripts using Tcl/Perl/Python to enhance team productivity

Benefits

  • Comprehensive health and wellness benefits
  • Retirement savings options
  • Performance-based incentives
  • Flexible work arrangements
  • Professional development opportunities
  • Employee discounts and perks
Full Job Description
Responsibilities

THE ROLE:

As part of AMD's S3 (Semi-Custom) organization, you will work within the Physical Design integration team to translate SoC RTL into a full-chip floorplan, enabling downstream implementation and first-pass silicon success. This role operates at the intersection of architecture, RTL, DFT/DFX, and physical design, with a primary focus on defining chip-level structure early in the design cycle. It is a highly hands-on, execution-driven role requiring deep expertise in full-chip floorplanning and physical design.

THE PERSON:

You are a hands-on physical design engineer with strong experience in full-chip floorplanning and SoC implementation. You are comfortable working across teams, driving early-stage implementation decisions, and translating design intent into practical physical structures. You bring strong ownership, problem-solving ability, and consistently deliver high-quality results in fast-paced, technically complex environments.

KEY RESPONSIBLITIES:
  • Own full-chip floorplanning (partitioning, macro placement, integration)
  • Translate RTL  full-chip floorplan (chip structure, block definition)
  • Plan pins, feedthroughs, and bus topology (incl. source-synchronous interfaces)
  • Define repeater strategy for timing and signal integrity
  • Optimize floorplan for timing, power, and area (PPA)
  • Run feasibility / tradeoff analysis for floorplanning decisions
  • Collaborate with RTL, architecture, DFT/DFX, and PD teams
  • Use tools like Fusion Compiler / Innovus for implementation
  • Build automation (Tcl / Perl / Python) to improve execution

PREFERRED EXPERIENCE:
  • Experience in SoC physical design with successful tapeouts
  • Strong ownership of full-chip floorplanning (partitioning, macro placement, integration)
  • Solid understanding of physical design flows and impact on timing, power, and implementation
  • Hands-on experience with Fusion Compiler or similar tools (e.g., Innovus)
  • Experience with feedthrough planning, bus topology, and timing-aware floorplanning
  • Understanding of SoC architecture (e.g., AXI, source-synchronous interfaces, test)
  • Proven collaboration with RTL, IP, DFT/DFX teams
  • Scripting skills (Tcl, Perl, Python, or Shell) for automation
  • Experience with large-scale SoC designs and low-power considerations
  • Experience improving design productivity through automation or advanced methods


ACADEMIC CREDENTIALS:

  • Bachelor's or master's degree in electrical engineering, computer engineering, or related field preferred


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Qualifications

Benefits offered are described: AMD benefits at a glance.

About Advanced Micro Devices, Inc

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Learn more about Advanced Micro Devices, Inc
Size
15,500 employees
Market Cap
$100.9 billion
Industry
Manufacturing & Automotive
Net Income
$2.4 billion
Founded
1969
5 Year Trend
+30.9%
Revenue
$9.7 billion
NASDAQ
AMD
* Ladders Estimates

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