Emulation Engineer

Eridu AI

$185K — $250K *
Technical Services
5 - 7 years of experience
Job Overview by Ladders

Qualifications

  • Bachelor's in Electrical/Computer Engineering with 7+ years of experience, or Master's with 5+ years.
  • Strong background in ASIC logic/RTL design and emulation model development.
  • Proficiency in Verilog/SystemVerilog, C/C++, Python, and Unix Shell scripting.
  • Experience with emulation platforms like Palladium, Veloce, Zebu, or FPGA prototyping.
  • Familiarity with emulation tools including BFMs and hybrid environments.

Responsibilities

  • Develop and deliver emulation models from RTL designs.
  • Plan and execute simulation acceleration and emulation activities.
  • Design high-performance transactors and emulation testbenches.
  • Drive methodologies for hardware verification and software development.
  • Analyze emulation results and identify performance regressions.
  • Conduct power measurements and evaluations on emulation platforms.
  • Collaborate with vendors to debug issues and enhance emulation capabilities.

Benefits

  • Collaborative and cross-functional work environment.
  • Opportunity to work with industry-standard tools and methodologies.
  • Focus on performance evaluation and optimization in hardware development.
  • Engagement in innovative pre-silicon environments and emulation technologies.
Full Job Description
Position Overview

We are seeking a highly skilled and motivated Emulation Engineer to join our hardware development team. The ideal candidate will be responsible for building and deploying emulation and FPGA models from RTL designs using industry-standard tools and methodologies. This role involves close collaboration with cross-functional teams including design, software, firmware, and validation to accelerate hardware verification and software development.

Responsibilities
  • Develop and deliver emulation models from RTL using synthesis, partitioning, and routing tools.
  • Plan and execute simulation acceleration, emulation, and prototyping activities aligned with project milestones.
  • Design and implement high-performance transactors and emulation testbenches using SystemVerilog and C/C++/DPI.
  • Drive emulation methodologies for hardware verification and software/firmware development.
  • Build system-level use cases for execution on emulators and support platform bring-up.
  • Analyze emulation results, identify performance regressions, and triage issues.
  • Conduct power measurements and performance evaluations on emulation platforms.
  • Maintain and enhance emulation CI infrastructure to support autonomous performance exploration.
  • Collaborate with vendors to debug issues and deploy new emulation capabilities.
  • Interface with design, validation, and software teams to optimize emulation environments and workflows.
Qualifications
  • Bachelor's degree in Electrical/Computer Engineering with a minimum of 7+ years of relevant experience, or Master's degree with 5+ years of experience.
  • Strong background in ASIC logic/RTL design and emulation model development.

Required Skills

  • Proficiency in Verilog/SystemVerilog, C/C++, Python, and Unix Shell scripting.
  • Experience with emulation platforms such as Palladium, Veloce, Zebu, or FPGA prototyping.
  • Familiarity with emulation tools and methodologies including BFMs, transactors, and hybrid environments.
  • Ability to debug hardware issues using waveforms, logs, and trace dumps.
  • Experience with CI/CD tools (e.g., Jenkins, GitLab CI) for automation and integration.
  • Excellent problem-solving, debugging, and analytical skills.

Preferred Skills

  • Experience in building workloads for pre-silicon environments.
  • Knowledge of emulation performance optimization techniques.
  • Exposure to system-level use case development and power/performance analysis.
  • Experience with computer networking protocols such as Ethernet.
  • Experience with network test equipment such as Ixia/Spirent traffic generators.



The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.

The pay range for this role is:

185,000 - 250,000 USD per year (San Francisco Bay Area )

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