Opportunity Overview Act as a digital functional verification technical lead responsible for the planning, strategy, and execution of challenging FPGA verification projects. Provide technical leadership for large, cross-site verification teams. The position requires interfacing with other functional groups (e.g. hardware, software, applications).
All About You We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you're ready to join us in this mission, take a closer look at the minimum criteria for the position.
- Master's Degree or equivalent in Electrical Engineering/Computer Engineering/Computer Science or closely related field with a minimum of 10 years of relevant work experience OR Bachelor's Degree or equivalent in Electrical Engineering/Computer Engineering/Computer Science or closely related field with a minimum of 12 years of relevant work experience
- Experience with verification planning and testbench architecture
- Experience with complete functional verification cycle from Design Specification Review to verification closure
- Proficient with System Verilog Constraint Random Testing, Assertions and Functional Coverage driving functional verification
- Expertise with UVM testbench development and Verification IP integration
- Experience with Reference models development and integration
- Knowledge of at least one of the following protocols/technologies: Ethernet, PCIe, AXI, MIPI, DRAM, FLASH
- Experience with regression failures analysis
- Experience with verification progress tracking
- Experience writing automation scripts (e.g. Makefiles, shell programming, TCL, Perl, Python)
- Experience working with revision source control (e.g. clearcase, git, svn)
- Ability to track and bring issues to closure. Detailed oriented. Excellent planning and organizational skills.
- Experience leading verification team
- Experience working with teams located in different time zones
- Experience mentoring junior engineers
Desired (but not required) skills/experience:
- Experience in FPGA design implementation with System Verilog
- Experience in verification of Automated Test Equipment functionality
- Static and/or dynamic Formal Verification
- Experience with GVP source control continuous integration tool
Compensation: The base salary range for this role is $154,900 - $247,800. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.
Incentive Plan: This job is eligible for discretionary bonus(es) based on financial performance.
Benefits:Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more. Please click here to see details
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