Req ID: 140258
Region: Americas
Country: USA
State/Province: Texas
City: Richardson

Summary

The DFT and Test Engineer runs the testability review inside the design phase. This role is responsible for checking test point access, boundary scan chains, debug access, and provisioning access against established DFT rules, while modeling coverage against the MTRS before layout freeze. Operating at the intersection of Hardware, Software, Firmware, and Test Operations, this position acts as the crucial gatekeeper for testability as an inherent design property and supports functional test definition and early build debug for the assigned site.

Note: This position focuses strictly on testability as a core design property and is not a Test Development or Fixture Design role.

Detailed Description

• Design Reviews: Review schematic and layout against the DFT rule set before freeze, raising findings alongside supporting evidence behind the rule.
• Coverage Modeling & Verification: Model structural and functional coverage to report gaps against the MTRS, and verify achieved coverage on the first fixture while recording differences against initial claims.
• Issue Disposition: Collaborate cross-functionally with schematic/layout engineers, software/firmware teams, the program TRL, site test engineering, and the DFT manager to resolve coverage gaps via test point additions, chain corrections, or agreed alternatives.
• Build & Debug Support: Support functional test definition and early build debug in tandem with the Test Readiness Lead (TRL) and on-site test SMEs.
• Continuous Improvement: Propose DFT rule changes derived from test escapes and fixture rework feedback to drive ongoing design standards.
• Ownership & Performance: Own key deliverables-including testability reviews, coverage models against MTRS, DFT findings with formal dispositions, achieved coverage evidence documentation, and rule change proposals. Performance is measured on first-fixture designed-in coverage, pre-freeze closed findings, test escape rates, and repeat findings.

Knowledge/Skills/Competencies

• Strong technical expertise in Design for Testability (DFT) concepts, checking test point access, boundary scan chains, debug access, and provisioning access.
• Proven hands-on proficiency with Boundary Scan, In-Circuit Testing (ICT), and coverage analysis tooling.
• Solid capability in modeling structural and functional test coverage against coverage standards (e.g., MTRS).
• Excellent collaborative problem-solving skills to disposition hardware and software findings across multi-disciplinary teams.
• Strong cross-functional communication skills to work effectively with schematic, layout, software, firmware, and test engineering stakeholders.

Physical Demands

• Duties of this position are performed in a normal office environment.
• Duties may require extended periods of sitting and sustained visual concentration on a computer monitor or on numbers and other detailed data.
• Repetitive manual movements (e.g., data entry, using a computer mouse, using a calculator, etc.) are frequently required.
• Occasional travel may be required.

Typical Experience

• 4 to 8 years of experience in Design for Testability (DFT) or Test Engineering in a complex electronics environment.

Typical Education

• Bachelor's degree in Electrical Engineering, Electronic Engineering, or a related technical discipline.

Notes

This job description is not intended to be an exhaustive list of all duties and responsibilities of the position. Employees are held accountable for all duties of the job. Job duties and the % of time identified for any function are subject to change at any time.

This location is a US ITAR facility and these positions will involve the release of export controlled goods either directly to employees or through the employee's movement within the facility. As such, Celestica will require necessary information from all applicants upon an applicant's acceptance of employment to determine if any export control exemptions or licenses must be filed.