Design Verification Engineer MAHIN-JOB-35440

Keylent, Inc.

• $130K — $150K *
Folsom, CA 95630In-Person
Technical Services
8 - 10 years of experience
Reposted 2 days ago
Be an Early Applicant
Job Overview by Ladders

Qualifications

  • 8-15 years of professional experience in design verification engineering
  • Proficiency in SystemVerilog and UVM methodologies
  • Strong background in developing Testbenches
  • Experience with debugging and troubleshooting hardware and software
  • Knowledge of full-chip and SoC simulation processes
  • Familiar with subsystem verification, particularly controllers and PHY components
  • Experience with standards like DDR5, LPDDR, PCIe, Ethernet, UCIe is a plus

Responsibilities

  • Utilize hands-on experience with SystemVerilog, UVM, and Testbench for verification
  • Perform debugging and troubleshooting to efficiently resolve issues
  • Conduct full-chip and SoC simulations for design validation
  • Demonstrate expertise in subsystem verification for controllers and PHYs
  • Verify bus interfaces and controllers for seamless integration
  • Focus on the verification of advanced subsystems/IPs for cutting-edge technology

Benefits

  • Full-time employment opportunity
  • Opportunity to work in a collaborative team environment
  • Onsite work model from day one
  • Engage with cutting-edge technologies in semiconductor design
Full Job Description
Design Verification Engineer MAHIN-JOB-35440
Location: Folsom, CA,
About the Role and Job:

Design Verification Engineer (8-15 Years Experience)
  • Work Location - Folsom, CA USA (1st Day onsite)
  • Max Salary Pay is 130 -150K -Only Full Time
  • Number of positions - 4

PW ID :TechM134072

Key Responsibilities:
  • Utilize hands-on experience in SystemVerilog, UVM, and Testbench development to facilitate the verification process.
  • Perform thorough debugging and troubleshooting to identify and resolve issues efficiently.
  • Conduct full-chip and SoC simulations to validate design functionality and performance.
  • Demonstrate expertise in subsystem verification, encompassing controllers and PHY components.
  • Verify bus interfaces, controllers, and PHYs to guarantee seamless integration and functionality.
  • Ideally, possess experience with subsystems/IPs such as DDR5, LPDDR, PCIe, Ethernet, UCIe.
* Ladders Estimates

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