Design Verification Engineer

Cerebras Systems

$190K — $230K *
Technical Services
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • Great debugging and problem-solving skills
  • Deep knowledge of SystemVerilog testbench, DPI, and UVM
  • Excellent programming skills in software engineering, including object-oriented design
  • Experience in developing scalable and portable testbenches
  • Familiarity with verification methodologies and tools like simulators and coverage collection
  • Proficient in scripting languages, specifically Python or Perl
  • Good interpersonal skills and an ability to collaborate effectively
  • 3+ years of design verification experience

Responsibilities

  • Collaborate with architects, designers, and engineers to ensure high-quality silicon designs
  • Develop and implement detailed verification strategies and coverage plans
  • Create reusable verification methodologies and components like checkers and assertions
  • Run tests, manage regressions, and troubleshoot test failures
  • Engage with cross-functional teams including architecture and firmware for effective validation
  • Analyze and debug issues across simulation and silicon phases
  • Enhance verification infrastructure and flows for better efficiency
  • Contribute to best practices and the evolution of verification methodologies

Benefits

  • Opportunity to work on groundbreaking advancements in AI
  • Collaborative work environment with cross-functional teams
  • Location in Sunnyvale, CA, a hub for tech innovation
  • Potential for bonus and equity compensation based on performance
Full Job Description
Key Responsibilities
  • Work with architects, designers, post silicon and software engineers to ensure a high-quality design that works for silicon.
  • Develop and implement verification strategies, detailed tests and coverage plans based on micro-architecture.
  • Create verification methodologies and reusable environments, including components such as stimulus, checkers, assertions, and coverage.
  • Implement tests, manage regressions, gather coverage, and debug test failures.
  • Collaborate with cross-functional teams including architecture, RTL design, physical design, firmware, and validation.
  • Analyze and debug complex issues across simulation, emulation, and silicon bring-up phases.
  • Continuously enhances verification infrastructure and flows to improve efficiency and quality.
  • Contribute to the evolution of the overall verification methodology and best practices across the organization.

Skills and Qualifications
  • Great debugging and problem-solving skills.
  • Deep knowledge of SystemVerilog testbench, DPI and UVM.
  • Excellent programming skills and knowledge of software engineering practices including object-oriented design.
  • Experience developing scalable and portable testbenches and components.
  • Experience with verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection, and gate level simulations.
  • Proficient in scripting languages such as Python or Perl.
  • Good interpersonal skills and the ability to work as a standout colleague are a must.
  • Extremely self-motivated and eager to solve problems
  • 3+ years of Design Verification experience.

Desired Skills and Qualifications
  • Knowledge of pipelined processor architecture.
  • BS or MS in Computer Science or Electrical Engineering.
  • 3+ years of hands-on Design Verification experience.

Location: Sunnyvale, CA

The base salary range for this position is $190,000 to $230,000 annually. Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.

Apply today and become part of the forefront of groundbreaking advancements in AI!

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