Full Job Description
Contribute to the development of efficient architectures and contribute to ASIC Architecture, design and verification Understand our in-house IPs needed and how they need to be integrated, connected and verified Drive the top-level architecture definition and develop the necessary RTL Drive the chip-level integration, verification plan development and verification Supervise the RTL-to-GDS flow and assist with synthesis and timing closure Support the test program development, chip validation and chip life until production maturity Work with FPGA engineers to perform early prototyping Support hand-off and integration of blocks into larger SOC environments Assist with Algorithm analysis, verification and improvement Contribute to ASIC digital architecture, design and verification Ability to communicate clearly.
