Meta's silicon engineering team is building custom infrastructure silicon to power the compute demands of AI, data center, and next-generation hardware platforms. As an ASIC Engineer focused on Physical Design, you will drive the physical implementation of custom ASICs from floorplanning through tapeout, working across a full-custom silicon design flow. In this role, you will collaborate closely with RTL design, verification, and package engineering teams to deliver high-performance, power-efficient silicon that underpins Meta's infrastructure at scale.
Responsibilities
Execute physical design tasks including floorplanning, placement, clock tree synthesis, routing, and timing closure for custom ASIC designs
• Perform static timing analysis and work to resolve setup and hold violations across design corners and operating conditions
• Collaborate with RTL and logic design engineers to ensure design-for-physical-implementation guidelines are met early in the design cycle
• Develop and refine physical design scripts and methodologies to improve automation, quality of results, and turnaround time
• Conduct power analysis and implement power optimization strategies including clock gating, multi-voltage domain partitioning, and IR drop mitigation
• Run and interpret physical verification signoff checks including DRC, LVS, and ERC to ensure design compliance with foundry rules
• Partner with package and board engineers to define bump maps, power delivery networks, and IO ring constraints
• Contribute to the development and documentation of physical design flows, best practices, and reusable block-level methodologies
• Analyze and resolve congestion, signal integrity, and electromigration issues across hierarchical design blocks
Minimum Qualifications
• Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta
• 2+ years of experience in ASIC physical design, including hands-on work with placement, clock tree synthesis, routing, and timing closure
• Experience with industry-standard physical design EDA tools such as Synopsys IC Compiler, Cadence Innovus, or equivalent
• Experience performing static timing analysis using tools such as Synopsys PrimeTime or equivalent
• Experience with physical verification flows including DRC and LVS signoff using Calibre or equivalent tools
• Experience scripting in Tcl, Python, or shell to automate physical design tasks and flows
Preferred Qualifications
• Experience with advanced process nodes (7nm or below) and associated design rule complexity
• Familiarity with low-power design techniques including multi-voltage domains, power gating, and dynamic voltage and frequency scaling
• Experience with hierarchical physical design methodologies for large, multi-million gate ASIC designs
• Exposure to custom data center or infrastructure silicon design from block-level implementation through tapeout
