About the role:Avicena is seeking a talented and detail-oriented ASIC Design Verification (DV) Engineer to join our chip design team. You'll play a crucial role in ensuring the functional correctness, performance, and robustness of our high-speed, low-power digital integrated circuits (ICs) for groundbreaking silicon photonics and optical interconnect solutions. This position requires strong expertise in verification methodology and a commitment to quality.
Responsibilities:- Testbench Development: Develop comprehensive and reusable verification environments (Testbenches) from scratch using advanced methodologies like UVM (Universal Verification Methodology).
- Verification Planning: Work closely with the architecture and design teams to define and execute thorough verification plans, including feature lists, test strategies, and coverage goals.
- Test Case Creation: Develop constrained-random, directed, and stress tests, as well as necessary sequences, scores, and functional coverage models.
- Functional Debugging: Execute simulations, analyze results, and effectively debug complex functional failures, working with design engineers to identify and resolve root causes.
- Coverage Closure: Drive functional and code coverage closure, identifying coverage holes and implementing targeted tests to achieve tape-out quality.
- Regression Management: Maintain and manage regression suites, optimizing simulation speed and efficiency.
- Formal Verification: Utilize formal verification techniques to prove correctness for critical design properties, such as clock domain crossing (CDC) and complex state machines.
- Scripting and Automation: Develop and maintain automation scripts (e.g., in Python or Perl) to enhance the verification flow and improve efficiency.
Qualifications:- Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- Experience: 3+ years of professional experience in ASIC/SoC design verification.
- UVM Expertise: Strong proficiency and hands-on experience in building and deploying reusable verification environments using SystemVerilog and UVM.
- Verification Languages: Expertise in SystemVerilog, and knowledge of scripting languages like Python or Perl.
- Tool Proficiency: Experience with industry-standard EDA simulation and debug tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa).
- Coverage Driven Methodology: Solid understanding of constrained-random verification and functional/code coverage analysis.
- Debugging Skills: Excellent analytical and problem-solving skills with a proven ability to debug complex digital logic and verification environments.
- Preferred (Nice to Have):
- Experience verifying high-speed interfaces, SerDes, or communication protocols like Ethernet and PCIe.
- Exposure to forward error correction (FEC), scrambling, and other digital data communication techniques.
- Knowledge of formal verification tools (e.g., Synopsys VC Formal, Cadence JasperGold).
- Familiarity with low-power verification techniques.
- Experience with hardware description languages (HDL) like Verilog/SystemVerilog for basic design understanding.
- Exposure to physical layer (PHY) or mixed-signal verification concepts.
