Responsibilities

THE ROLE:

The AMD IOHUB Team (part of the NBIO organization) is looking for an ASIC Design Engineer to join our growing team. We develop leading-edge I/O connectivity and virtualization technologies powering data center and machine learning workloads. This team is part of the development for tomorrow’s client, server, embedded, graphics, and semi-custom chips. You will be involved in all aspects of IP design starting from architecture to requirements to execution. As a key contributor to the success of AMD’s IP, you will be part of a leading team to drive and improve AMD’s abilities to deliver the highest quality, industry leading technologies to market. The NBIO Team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

THE PERSON:

The ideal candidate is a detail-oriented and driven ASIC design engineer who enjoys solving complex technical challenges and seeing work through to successful completion. You combine strong analytical and problem-solving abilities with excellent communication and collaboration skills, allowing you to work effectively across globally distributed engineering teams. You are proactive, adaptable, and comfortable navigating ambiguity while maintaining a focus on quality and execution.

You bring a strong sense of ownership, accountability, and professionalism to your work, along with the ability to build trusted relationships with peers and stakeholders. Success in this role requires sound technical judgment, effective time management, and the ability to clearly communicate technical concepts, status, and risks to diverse audiences. You are a continuous learner who embraces feedback, seeks opportunities to improve processes, and enjoys mentoring others while remaining hands-on and engaged in solving challenging engineering problems.

In this role, you will work closely with IP and SoC design teams across the globe to drive design quality, support integration, and help resolve complex synthesis, timing, and physical implementation challenges. You will have the opportunity to contribute to high-impact technology, collaborate with multi-disciplinary engineering teams, and help advance AMD's ability to deliver industry-leading products to market.

KEY RESPONSIBILITIES:

• Understand the functional and performance requirements of the IOHUB within various SOCs
• Drive IP/SOC design infra decisions to ensure consumption within the context of the SOC.
• Provide guidance and/or act as a liaison between IP and SOC design teams for synthesis and physical layout issues
• Scope requirements and resources to meet project schedules
• Provide hands on leadership of a small team of Engineers/Engineers in Training as required to meet program development goals
• Signoff IP quality for delivery into SOC
• Effectively communicate with multi-disciplined teams located across the globe
• Gather, attend and present into technical status meetings on a weekly/bi-weekly basis

PREFERRED EXPERIENCE:

• Proven ASIC design experience, RTL design experience on large ASIC development projects
• Strong background working with industry standard synthesis tools, flows and back end timing closure(e.g. Formality, CDC & Linting tools, Design Compiler/FX etc)
• Strong background in Verilog and System Verilog
• Strong analytical skills and attention to detail
• Excellent written and communication skills
• Understanding of the IP integration and interactions within an SOC
• Must be a self-starter and able to independently drive tasks to completion
• Demonstrates the ability to debug issues and quickly identify viable solutions
• Team player with proven leadership skills

ACADEMIC EXPERIENCE:

• Bachelor of Science Degree in Electrical Engineering, Computer Science, or Computer Engineering

LOCATION: Markham, ON, Vancouver, BC

This role is not eligible for visa sponsorship.

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Qualifications

Benefits offered are described: AMD benefits at a glance.

This posting is for an existing vacancy.