About The RoleJoin our close-knit physical design team where you'll excel in synthesizing, placing, and routing high speed designs. Experience the full spectrum of physical design and implementation, collaborating closely with the RTL team and integrating these blocks seamlessly into the full-chip architecture.
Skills & Qualifications:- 10+ years of physical design & physical verification experience.
- Strong knowledge of block level and full-chip physical verification methodology.
- Strong experience in block/subsystem timing closure.
- Expert at optimizing for the best power/performance and area.
- Experience with the complete physical design flow.
- Expert with ICV or Calibre tools resolving block and full-chip DRC and LVS issues.
- Expert with IR/EM analysis and resolution.
- Strong background in STA, constraint drafting and timing convergence at block, partition and fullchip.
- Should demonstrate and raise the bar for "ownership", "deep dive" and should demonstrate strong fundamental understanding of PD concepts.
- Good understanding of full chip floor planning and integration.
- Strong ability in scripting languages like Tcl and Python. Ability to make flow enhancements.
- Demonstrated ability to work with RTL teams to optimize for physical design.
- Skills in Design Compiler, Fusion Compiler, ICC2 or similar physical design tools.
- BS or MS in Electrical Engineering.
Preferred:- Knowledge of CPU/GPU design a plus.
- Block/partition PD, PDV, IR would be good to have.
- Knowledge of Synopsys tool suite is a plus.
The salary range for this position is $150,000 - $250,000 annually. Actual compensation will be determined based on factors such as experience, skills, qualifications, and location.
