Lead the architecture of high-performance compute and memory subsystems for cutting-edge IPU/DPU platforms. Drive system-level optimization in hyperscale environments, ensuring top-tier performance, power efficiency, and scalability across complex integrations.

Engineer next-gen compute and memory architectures for high-performance IPU/DPU platforms, optimizing performance, power, and scalability in multi-domain environments while collaborating across teams for system-level integration.

Collaborate with cross-functional teams to architect high-performance compute and memory subsystems for next-gen platforms. Drive system performance, power efficiency, and scalability in complex SoC designs while ensuring robust integration across subsystems.

Explore the future of high-performance memory systems by leading the architecture of compute complexes and memory subsystems for advanced IPU/DPU platforms, ensuring optimal performance, scalability, and seamless integration in hyperscale environments.

Contribute to the validation of cutting-edge SerDes technologies, ensuring top-notch functionality and reliability. Collaborate with cross-functional teams to solve complex validation challenges and innovate next-gen hardware solutions.