Take ownership of the CAD environment by enhancing the Cadence Virtuoso platform, collaborating with vendors, and integrating AI solutions to improve user experience and workflow efficiency in complex design processes.

Oversee post-silicon validation of memory subsystems, ensuring performance and stability through hands-on debugging and collaboration with cross-functional teams to resolve complex issues.

Join our dynamic team as you lead the development of FullChip constraints and timing closure, collaborating with world-class engineers and architects to deliver cutting-edge SOC designs while mentoring the next generation of design professionals.

Drive the modernization of design infrastructure and AI solutions, enhancing production workflows in silicon development. Collaborate with cross-functional teams to ensure reliability in AI-enabled methodologies that support engineering excellence.

Advance your career by leading physical design implementation for complex AI and HPC products. Drive execution and quality, optimize methodologies, and partner with cross-functional teams to deliver cutting-edge silicon solutions.