Wireless RTL Design Engineer - Power Management

5 - 7 years experience  •  Business Services

Salary depends on experience
Posted on 09/21/17
Santa Clara, CA
5 - 7 years experience
Business Services
Salary depends on experience
Posted on 09/21/17

Wireless RTL Design Engineer - Power Management

  • Job Number: 113051251
  • Santa Clara Valley, California, United States
  • Posted: Sep. 19, 2017
  • Weekly Hours: 40.00

Job Summary

In this highly visible role, you will be at the center of a silicon design group with a critical impact on getting functional products to hundreds of millions of customers quickly.

Key Qualifications

  • •5 or more years of experiences in SoC integration, ASIC Low Power related design
  • •Proficiency in ASIC logics design
  • •SoC power management design experience
  • •SoC level power related design verification experience
  • •Understanding of ASIC low power design techniques, e.g. Power analysis, UPF, VCLP
  • •SoC level clock mesh / reset design experience is a plus
  • •Proficient in Shell and Perl scripting, Python skills are a plus
  • •SoC top level integration experience is a plus
  • •System architecture knowledge is a plus
  • •Strong problem solving skills

Description

•Complex SoC low power design, analysis and implementation •Writing specifications and other documents •IP integration, RTL logic design, and DV support •Running tools to ensure lint-free and CDC clean design •Synthesis and timing constraints

Education

MSEE, PhD preferred

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