We are seeking multiple ASIC Verification Engineers for various clients in the Bay.
Are you interested in working on an industry leading networking chip? Join these team of veterans as they innovate in numerous areas.
? Develop the architecture for a functional verification environment.
? Write a verification test plan using random techniques and coverage analysis and working with designers to ensure it is complete.
? Build a constrained random environment for various functional blocks as well as for full chip testing.
? Debug failures and work with designers to resolve issues.
? Understand and expose to all design blocks as well as full-chip architecture of a product.
? Strong programming skills using C++ and Verilog.
?Experience with writing a detailed test plan and building a sophisticated directed random verification environment.
? Working knowledge in one or more of the following: Processor architecture, Networking, SOC components, SOC inter-connect busses and memory interfaces.
? BSCS/EE or equivalent required with 6-15years of verification experience
Verification engineers, verification, UVM, OVM, VMM, System verilog, Test bench, functional, random, constrained