Are you interested in working on an industry leading networking chip..how about Leading edge wireless SOC's? Join these team of veterans as they innovate in numerous areas.
- Develop the architecture for a functional verification environment.
- Write a verification test plan using random techniques and coverage analysis and working with designers to ensure it is complete.
- Build a constrained random environment for various functional blocks as well as for full chip testing.
- Debug failures and work with designers to resolve issues.
- Understand and expose to all design blocks as well as full-chip architecture of a product.
- Engage with multiple leading-edge product lines.
- Strong programming skills using C++ and Verilog.
- Experiencewith writing a detailed test plan and building a sophisticated directed random verification environment.
- Working knowledge in one or more of the following: Processor architecture, Networking, SOC components, SOC inter-connect busses and memory interfaces.
- Experience in working with ASIC verification tools.
- Coding in scriptinglanguages like Perl, Python, Tcl & UNIX Shell etc.
- MSCS/EE or equivalent with4-15years of logic verification experience.
- Experience in System Verilog is strongly desired
- Experience in UVM or OVM methodology
- Exposure to DFT features and verification tasks is a plus.
- Good understanding of Linux O.S. and networking protocols is a plus.
- Diligent, detail-oriented, and willing to take initiative
- Ability to handle assignments with minimal supervision.
- Self-driven and a good team player.
- Must have effective interpersonal and teamwork skills
- Excellent communication skills
- Ability to interface internally and externally withother departments.
- Has an inherent sense of urgency and accountability.
- Grounded, detail-oriented.
- Must have the ability to multi-task in a fast paced environment.
- Demonstrates good analysis and problem-solving skills
- BSCS/EE or equivalent requiredwith6-15years of verification experience
Verification engineers, verification, UVM, OVM, VMM, System verilog, Test bench, functional, random, constrained