Test Development Engineering Manager

eSilicon   •  

San Jose, CA

11 - 15 years

Posted 245 days ago

This job is no longer available.

Position Summary

Reporting to the Director of Test Engineering, this hand-on semiconductor test engineering professional is being sought to lead a test development engineering team to support new product introduction and high volume manufacture activities for WS and FT testing to meet all quality, reliability, yield and cost requirements.

Primary responsibilities are working with DFT, IP Test team defining test plan structure, tools used for pattern conversion and analysis, pattern debug, drive automation through software and tools.

Responsibilities include:

  • Lead a team to support test development activities including test plan generation, HW design, pattern conversion, ATE debugging, production document review, and customer interface
  • Setup test methodology library
  • Improve test development process
  • Standardize and simplify pattern conversion
  • Automate test program generation
  • Work closely and effectively with global team members and customers
  • Engage and interface vendors for HW design, pattern conversion and program automation
  • Drive continuous improvement in test time reduction, improve test coverage and test program quality


Experience and Background Requirements include

  • BSEE/MSEE with 10+ years developing ATE test solutions for SOC products with high speed digital (SerDes, DDR, PCI) interfaces, Memory, PVT, PMU (LDO..) and Analog (ADC, DAC, PLL..) functionalities
  • Must be familiar with ATE specification, configuration and programming on Advantest SmartScale, PinScale, 93K platform
  • Must be familiar with pattern tools like TSSI, TestInsight, Velocity and VTRAN
  • Good DFT knowledge and test methodology to improve testability, throughput and to reduce test cost
  • Competency in programming with Scriptinglanguages (ie, Perl/Python) and high level languages (ie, C/C++ or Visual Basic.)
  • Demonstrated Proficiency with strong hands-on test development and debug skills
  • Proven ability to interface with variety of global teams and customers
  • Excellent communication skills, including written and spoken English
  • Understanding of high performance digital SerDes, DDR, test methodologies and sampling theorem

Preference will be given to those who also possess experience :

  • on Teradyne UltraFlex, j750, iFlex platform
  • on direct dock WS testing, 2.5D testing and multiport test solution
  • with Cadence Allegro tool in ATE PCB design
  • in RF testing