Technical Lead ASIC/ Layout Design Engineer

Advanced Micro Devices   •  

Santa Clara, CA

Industry: Professional, Scientific & Technical Services


11 - 15 years

Posted 170 days ago

This job is no longer available.


Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.


1. Technical lead of five to eight senior level engineers
2. Tasks to include RTL Synthesis, Placement, Clock tree synthesis, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification and Sign Off
3. Identify complex technical problems, break them down, summarize multiple possible solutions, and lead the team in the right direction
4. Drive and hands-on flow development and scripting
5. Technical and schedule discussion with multi-site engineers and managers 


1. Over 10 years experience with BSEE/BSCS or 5+ years of MSEE or MSCE in ASIC Physical Design from RTL to GDSII
2. Excellent analytical and problem solving skills along with attention to details
3. Strong RTL analysis skills including Verilog, Timing Analysis and library understanding
4. Hands on experience in taping out 14nm, 16nm, 20nm, 28nm, 32nm, and/or 40nm SOC
5. Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics
6. Strong communication, Time Management, and Presentation Skills
7. Must be a self-starter, and be able to independently and efficiently drive tasks to completion
8. Ability to provide mentorship and guidance to junior and senior engineers, and be an effective team player


  • Bachelor, Master's or PhD degree in Electrical or Computer engineering.