Marvell is an industry leader in RAN infrastructure silicon solutions. In 5G, Marvell offers complete silicon platforms that enable all aspects of the digital processing domain. Marvell’s award winning OCTEON Fusion® family of 4G/5G baseband processors with a specific focus on 4G/5G layer 1 processing is the industry’s only macro cell merchant silicon available in the market. Marvell's RAN solutions enable incumbent suppliers and new market participants to deliver on the promise of next-generation wireless communications. This OCTEON Fusion’s Systems engineering team is expanding and is looking for the candidates with the following qualifications.
- Simulate, analyze and optimize bit accurate designs in comprehensive PHY Simulator under various RF imperfections and fading channels to meet performance requirements
- Work closely with ASIC design team to design HW block architecture, verify and validate optimized RTL implementation.
- Work with Modem SW design team to implement and verify assigned features on modem SoC
- Guide System Test to characterize and optimize modem performance in lab and on the field
- Technical support for customer to enable fast system development
- Must have at least 3 years of experience in developing physical layer algorithms for cellular wireless technology with at least 3 years of RAN algorithms for LTE/5G-NR.
- Theoretical background in Wireless Communications and Digital Signal Processing.
- Experience with wireless system regression test
- Expert level understanding of LTE, LTE-A and 5G Radio/PHY layer standards
- Hands-on experience with script development using languages such as Perl/Python as well as Linux scripting
- Experience in fixed-point PHY simulations using Matlab, C/C++ and performance evaluation is a plus.
- Expertise in practical design, implementation and verification of RAN algorithms: Massive MIMO, Beamforming, CoMP, RRM, AGC, Channel Coding, Channel Estimation, FO, TO etc. is a plus.
- Knowledge of O-RAN specifications in the Open RAN ecosystem is a plus
- Experience with real-time, embedded PHY SW implementation, Vector DSP programming, optimization and debugging is a plus.
- Experience in working with ASIC design team to guide RTL implementation, verification and validation is a plus
- Effective interpersonal and teamwork skills
- Excellent communication skills
- Good analysis and problem-solving skills
- Grounded, detail-oriented, always backs up ideas with facts
- Ability to multi-task in a fast paced environment
- Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience. OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience.