Staff Design Engineer
This individual will be responsible for the development of analog or mixed-signal CMOS IP that will be integrated into via-configurable arrays, possibly taking the role of IC project leader.
Tasks/responsibilities include: analog transistor/gate level design and simulation; chip architecture, floorplanning, and simulation; behavioral modeling of IP; custom layout/place and route/verification; lab evaluation.
- 10+ years experience in IC Design (8+ years with advanced degree, e.g. MSEE)
- Self motivated—requiring minimal supervision
- Excellent verbal and written communication skills.
- Theoretical and practical understanding of analog and/or digitalcircuit design
- Background in Verilog and/or VHDL
- U.S. Citizen or Green Card holder
- MSEE or appropriate advanced degree
- Automated place and route tool experience
- Static timing analysis experience
- Full-custom mixed-signal IC Layout experience