Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
Staff Analog/Mixed-Signal Layout Engineer
As a Staff A&MS Layout Engineer you will collaborate in the development of advanced analog integrated circuit designs using best-in-class Synopsys suite of tools. You will be working with local and global teams in developing layout for complex mixed-signal designs in the latest technology nodes. In your role you will be responsible for taking on product level ownership with technical expertise and skills. You will act as technical lead in critical development projects and have direct interaction with internal and external customers as organizational representative.
As a member of our Solutions IP Design Group you will be developing IP in various technology nodes and foundries for different customers in a fast paced and exciting design environment.
- In depth familiarity with layout of analog and mixed signal CMOS circuits
- Experience in development of SERDES subcircuit layout (ie. RX, TX, PLL, etc…)
- Experience in the following layout design techniques:
- Optimization for signal integrity (ie. clock/data routes, differential routing, shielding)
- Implementation of ESD design constraints, latch-up risk mitigation
- Familiarity with custom digital layout (logic cell layout and associated logic path routing)
- Layout design for reliability (ie. EM, IR, etc…)
- Design to optimize for parasitic layout effects (ie. matching, reliability, proximity effects, etc…)
- Familiarity in design for porting techniques
- Full custom analog layout design tool: Custom Compiler (or equivalent)
- Verification tools: ICV, Calibre, Star-RCXT, PERC
- Experience in working with Jira/Atlassian (or other such) tools
- Strong working knowledge of MS Office Suite of applications
- Exposure to scripting (ie. TCL, PERL, etc…)
- Typically requires an MSEE or BSEE with a minimum of 10+ years of related experience, with 2+ years of experience in a technical lead role.
- Has experience as technical layout design expert on fabrication flows and physical background behind layout design flows and techniques.
- Can work independently to work on complex issues where analysis of data requires and in-depth evaluation of variable factors.
- Can resolve a wide range of issues in creative ways as well as encouraging others to support a new solution or direction.
- Is able to perform in a project leadership role and contribute to complex design tasks in collaboration with analog circuit design and ASIC digital design teams.
- Can prepare and present technical layout design material for internal and external audiences.
- Represents team in cross-organizational initiatives and discussions.
- Acts in a mentorship role for junior peers to support training, review and enablement for growth and development.
- Has had direct interaction with management and senior personnel on layout design topics which require coordination across internal groups.