We are a leader in secure, intelligent wireless technology for a more connected world. Our integrated hardware and software platform, intuitive development tools, unmatched ecosystem and robust support make us the ideal long-term partner in building advanced industrial, commercial, home and life applications. We make it easy for developers to solve complex wireless challenges throughout the product lifecycle and get to market quickly with innovative solutions that transform industries, grow economies and improve lives. silabs.com
The candidate will be a technical contributor as part of an engineering team providing services and developing methodology and highly customizable flows for the backend physical design process, Netlist-to-Manufacturing.
- Provide design engineering services to business units - Perform specialized place and route tasks at the block and full chip level, including:
- Data preparation of custom macros for physical design flows
- Floorplanning and power grid construction
- Placement optimization
- Clock tree synthesis
- Routing optimization for timing and power closure
- DFM and chip finishing
- Parasitic extraction and timing/power analysis
- Work closely with the midend/synthesis designers to deliver the best overall quality of results.
- Work closely with the design engineers to understand the requirements of their SoC products and develop innovative Netlist-to-Manufacturing solutions for design and methodology challenges.
- Provide flow support including training, issue resolution, and solution deployment.
- Interface with EDA tool vendors to provide user support, evaluate & deploy new tools, and drive tools improvement and bug fixes.
- BS+ in Electrical Engineering or equivalent with 15+ years of related professional industry experience.
- Strong working knowledge and advanced skills in taping out complex mixed-signal, multi-power-domain SoC designs, including floorplanning, placement, CTS, routing and timing/power closure.
- Understanding of VLSI design fundamentals, including digital ASIC design, logic synthesis, Design for Manufacturing, high speed timing closure/signoff and ultra low power design techniques.
- Expert user of industry standard EDA tools for place and route, layout, parasitic extraction, and timing/power analysis (Innovus/Virtuoso/QRC/Tempus/Voltus preferred) with good working knowledge of scripting languages (Shell, Perl/Python, Tcl).
- Familiar with the performance signoff process, including timing/power signoff and gate-level simulation.
- Excellent written and verbal communication skills. Strong problem-solving skills with an innovative mindset.
We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.