Sr. SoC Design Verification Engineer
- Job Number: 113052973
- Santa Clara Valley, California, United States
- Posted: Sep. 19, 2017
- Weekly Hours: 40.00
In this role you will be responsible for and contribute to verifying high throughput complex SOCs, integrating multiple complex IP level DV environment into chip level DV, creating highly reusable best-in-class UVM TB, implementing effective coverage driven and directed test cases, deploying new tools, methodology to improve quality of tape-out readiness.
- •BS/MS in EE/CS with at least 10+ years of dedicated/hands-on ASIC DV experience in reusable verification methodology such as UVM, OVM, eRM, VMM, etc. with most recent experience in UVM and proven track record of working full ASIC cycle from concept to tape-out to bring-up.
- •Proven track record of taping out large SOC systems with embedded processor cores and hands-on verification experience of PCIe, Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment
- •In-depth knowledge and experience working with low power design, UPF integration, boot-up, power-cycling, HW/FW interaction verification
- •Should be a team player with excellent communication and problem solving skills and the desire to take on diverse challenges.
•Understand details of High Throughput SOC Architecture, standard SOC peripherals such as SPI, I2C, UART, Timer, DMA, memory management schemes, low power spec, multi-processor systems, DDR, PCIe, PLL, power up scheme. •Create coverage driven verification plans from specifications, review and refine to achieve coverage targets. •Architect UVM based highly reusable test benches and integrate complex multi-instance VIPs, sub-system test benches and test suites to SOC level, achieve targeted coverage, work with design, architecture, SW, FW and external IP delivery teams to effectively integrate and verify overall SOC design •Work closely with DV methodology architects to improve verification flow.
Typically requires MSEE with 10+ years of verification experience.