Sr. Silicon Performance Architect in Sunnyvale, CA

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Enterprise Technology   •  

8 - 10 years

Posted 8 weeks ago

Microsoft is a leader in design of world-class devices. Come join the dynamic Microsoft Silicon team. The team that is responsible for XBOX silicon and Hololens HPU continues to grow the architecture team to change the world again.

We are looking for a world-class Silicon Performance Architect to join our teams in Silicon Valley or Redmond. The successful candidate will be a motivated self-starter who will thrive in this highly technical environment.


As a member of the Microsoft's silicon architecture team, you will collaborate with experienced architects to directly impact future products thru:

  • Performance modeling and evaluation of existing and future designs
  • Defining and evaluating software and firmware optimizations
  • Workload & benchmark definition and development
  • Performance verification and model correlation
  • Competitive analysis and vendor evaluations


Minimum Requirements:

MS/Ph.D. in Electrical, Computer Engineering or Computer Science.

  • 7+ years of experience.
  • Proven track record of successful design of IPs and SoCs.
  • Experience with cycle-accurate, system and chip level performance modeling
  • Experience defining performance verification plans
  • GPU performance analysis, benchmarking and modeling along with GPGPU algorithm mapping desirable.
  • Image signal processing and multimedia evaluation desirable.
  • Technical leadership experience with a diverse array of highly skilled teams, including product definition, software teams, RTL design teams, verification teams and external vendors

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.