Sr. Packaging Engineer
5 - 7 years experience •
Job Description Microsemi is seeking a Sr. Packaging Engineer for our Engineering Services Group located in Camarillo, CA. The Engineering Services Group is responsible for delivering analog and mixed-signal IP to divisions within Microsemi. We work with leading edge CMOS processes to produce analog integrated circuits for storage and wireline applications. From T1/E1 to 56Gb/s SERDES, we enable technology that allows Microsemi's products to interface to the outside world.
The candidate will be engaged in the package design and layout. Duties will include, but not be limited to, the following:
* Conduct package routing feasibility and layouts for Microsemi high-speed products, especially (or including) for 2.5D and 3D integration
* Perform PCB breakout studies for ball map feasibility
* Perform thermal analysis, SI/PI/EMI analysis on the package.
* Make recommendations to board/package/die based on analysis
* This is a Corporate role, working for different business units, candidate should be able to communicate clearly and effectively via written email, meetings, presentations etc.
* Guide and assist design teams on creation of input data for package design flow Qualifications Required Qualifications
* Bachelor's or Master's Degree in Electrical Engineering
* 5+ years' experience in package and PCB design. Strong working knowledge/understanding of Advanced Packaging Processes
* Experience in routing high speed signals, SI, PI and EMI analysis
* Experience with EDA tools and flow for thermal and mechanical analysis. Familiarity with Cadence/Mentor tools
* Ability to learn on the job and adapt to new technologies/EDA tools and product requirements
* Capable of handling multiple tasks at once
* Customer oriented, with attention to detail
* Familiar with package design using Cadence APD
* Scripting in PERL or SKILL
* Familiarity with flip chip and wire bond package designs
* Familiarity with PCB design and BGA fanout issues
* Understanding of high speed and power routing rules/issues and familiarity with EDA tools (HFSS/Sigrity) for modelling and analysis