NXP Semiconductors N.V. (NASDAQ: NXPI) enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better, and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the automotive, industrial & IoT, mobile, and communication infrastructure markets. Built on more than 60 years of combined experience and expertise, the company has over 29,000 employees in more than 30 countries and posted revenue of $8.88 billion in 2019.
Automotive Microcontrollers & Processors (AMP) is a global leader in the design, manufacturing and marketing of microcontrollers (MCUs) and embedded processors in the automotive markets. These products include 32 and 64-bit MCUs and microprocessors. NXP is the world's No. 1 supplier of semiconductors to global auto manufacturers. We provide comprehensive design solutions, including software, development tools, application support, training, documentation and reference platforms, enabling our customers to rapidly go to market.
- Perform concept studies and provide direction in terms of performance, gate count and power for various digital designs.
- Write detailed design specification and test plans in close collaboration with architecture, circuit designers and verification engineers.
- Provide high-quality RTL description, including assertions, for the design. Formal tools and static checkers will be used to guarantee RTL quality.
- Perform all aspects of the SoC design flow from high level design to synthesis, Static Timing
- Perform ARM Core and SoC specific Digital IP integration at SoC level
- RTL integration for vendor driven IPs (PCie, ENET, DSP cores, GPU, VPU, CSI, DSI, DDR controller, USB, Display Controller)
- Run logic Synthesis and Static Timing using vendor driven tools
- Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking
Experience with the following tools:
- Synopsys VCS or Cadence RTL simulator, Design Complier (DC) or RTL Compiler (RC or Genus), Verdi Debugging tool
- Static Timing Tool: Prime Time or Tempus
- Spyglass LINT, CDC and RDC or Mentor Questa CDC/RDC
- BS or MS in Electrical eEgineering or Computer Engineering
- BS with 5+ or MS with 2-3 years of experience in high performance digital logic designs and integration
- Prior experience in Logic Design using Verilog or System Verilog, assertion writing, SoC Integration, familiarity with Perl/TCL/Python is a plus
- Design of state machines, data paths, arbitration and clock domain crossing logic
- Logic synthesis, timing constraints
- Preferred Qualifications: – Exposure to VLSI design/logic design, ARM Microprocessor or Chipset design methods & Computer Architecture, ARM or Arteris Interconnect
- Exposure to Synopsys and Cadence front end tools is a plus
- Good skill to RTL sign off checks (LEC, LINT, CDC, RDC, DRC). UPF and CLP expertise are plus.