In this critical role, you will be responsible for defining, implementing, and supporting the methodologies, flows, and tools necessary to ensure clean signal integrity across Apple silicon.
As a CAD engineer working on signal integrity verification, you will work closely with design teams, circuit teams and CAD groups to ensure that designs meet our signal integrity and performance goals.
In this exciting role on our team, you will:
- Define consistent analysis methodology, margins, and perform tool validation for signal integrity verification.
- Write and support flows around core gate-level noise and static timing analysis tools.
- Work closely with CAD and design teams to drive signal integrity closure efforts for multiple projects.
MS or BS Degree in technical discipline