Sr. ASIC / Layout Design Engineer

Advanced Micro Devices   •  

Markham, ON

Less than 5 years

Posted 246 days ago

This job is no longer available.

At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. 


Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.


We, Video HW IP/Solution Group at AMD Markham site, are looking for a Senior ASIC Design Engineer who will work in a newly established VCN integration and product team. The role will require the candidate to initially acquire background knowledge of VCN IP core, test suite, and integration / verification methodology. Subsequently the candidate will be responsible to integrate VCN IP for all discrete ASIC solutions, develop additional functional and performance tests, and perform verification at SOC level, adapting SOC tools/flow to IP environment, and work with extended global counterpart for delivering required VCN SOC solutions. The candidate is also the prime front-end verification contact between VCN IP and chip teams.



  • Create detailed specifications of VCN SOC DV and performance test plan.
  • Perform VCN integration and verification at chip level.
  • Develop or adapt test libraries, emulation model, and test cases from VCN IP environment.
  • Develop Verilog and C++ bus functional models for product specific features.
  • Design and implement test benches in Verilog, C/C++.
  • Develop or adapt, and verify VCN performance test at chip level.
  • Work with ASIC design team to debug test failures at IP and chip level.

Work on methodology of accelerating deployment verification at sub-system level


- Minimum BSEE/CE, or equivalent degree.

- 3+ years of hands-on design verification experience in ASIC product development.

- Strong C/C++ software development experience.

- Experience in Verilog, scriptingexperience (csh, perl, awk, etc.).

- Experience with simulation and other DV tools.

- SystemC, Vera, and Specman are good assets.

- Strong problem solving skills, and attention to details.
- Good interpersonal skills (verbal and written).
- An organized, enthusiastic self-starter, strong interest in hardware verification methodologies.

- Capable of working as an independent contributor and team member in global setting

Requisition Number: 63045