The candidate would participate on a team of design verification, architects and design engineers, working closely with other team members to understand and verify the functionality of the design within the context of the unit, block, and overall system. The candidate would be responsible for carefully documenting and executing test plans consisting of directed and random tests to be run under simulation and hardware acceleration. Experience with hardware modeling, assertions, and formal verification methods are valuable assets. The candidate would be expected to adopt evolving verification methodologies used in the industry as well as develop custom techniques to functionally verify increasingly complex IP designs within aggressive, market-driven schedules.
Education and Experience Required:
- Min. Bachelor of Science Degree in Electrical Engineering, Computer Science, or Computer Engineering.
- 5+ year(s) of proven verification experience on large ASIC development projects or equivalent embedded programming experience with a deep understanding of hardware architecture
- Very strong background in C/C++/OOO coding techniques
- Experience with Verilog and/or System Verilog
- Experience working with Cadence NCSIM, Synopsys VCS or equivalent
- Experience working with UVM, OVM or equivalent
- Experience with scripting languages, Ruby/Python/Tcl/BASH/etc.
- Working knowledge of UNIX/Linux operating systems and debug tools
- Interest in developing custom verification tools and driving new test methodologies
- Strong analytical skills and attention to detail
- Excellent written and communication skills
- Team player with proven leadership skills
- Understand the architecture of the Display IP and functional block being designed
- Build SystemVerilog and/or C/C++ models and test sequence libraires for simulation
- Build test bench and monitors for DUT
- Compose test and coverage plan, and validation vectors to ensure functional completeness
- Debug function/performance bugs of Display IP
Requisition Number: 56541