The Sr ASIC Design Engineer will work closely with internal interdisciplinary teams to help us build high-performance, power efficient chips for AI applications. You must be responsive, flexible and able to succeed within an open collaborative peer environment.
ESSENTIAL DUTIES AND RESPONSIBILITIES:
- Responsible for the architecture, micro-architecture and design of the chip control unit of our Machine Learning ASICs
- Ownership of the top-level netlist, selection and integration of IP, CDC, clocking, resets.
- Architect, implement and verify power management techniques, multiple voltage domains, isolation cells insertion.
- Architect and implement security solutions
- Collaborate with system software team on boot code and firmware development
- Guide and review verification of blocks owned
- Participate in silicon bring-up for blocks owned
- Coordinate design activities for block with Software and Systems teams
- BS in Electrical Engineering or Computer Engineer or related degree required; advanced degrees (MS, PhD) a plus.
- Expert level knowledge in control and boot subsystems of complex, high performance processors, GPU’s or application processors
- Expert in microcontroller peripherals including I2C/SMB, SPI, UART, ADC
- Experience with multiple clock domains and asynchronous interfaces
- Expert knowledge in clock and reset design, and implementation of complex ASIC power management systems with UPF
- 10+ years of meaningful industry experience and a background in high speed complex ASIC/SOC design
- Experience with all stages in the ASIC design flow including emulation, prototyping, DFT, Synthesis, timing analysis, floorplanning, ECO, bringup & lab debug, and ATE test development
- Experience in integrating ASIC IP into SOC
- Experience in Security and BootLoaders a plus
- Experience with industry standard EDA tools from Cadence, Synopsys or Mentor
- Expertise in developing firmware and system management software for high performance processors a plus
- Experience in designing tools and scripts for creating control and status register maps a plus
- Strong working knowledge of Verilog or SystemVerilog, C