What you do at AMD changes everything
At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center.
Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.
We, Video HW IP/Solution Group at AMD Markham site, are looking for a SMTS ASIC Design Engineer who will work within video IP teams. The role will require the candidate to take on block ownership, and drive corresponding block architecture, HW development effort to deliver current and next generation of video IP/solution. The candidate will also lead and work collaboratively with extended block members to enable feature solutions among global video teams.
- Assume full responsibility as one of RTL block owner in VCN IP.
- Responsible for block architecture, and own all front-end HW engineering and design tasks
- Work with existing RTL team to deliver current and next generation of video IP/solution.
- Lead and drive resolution in synthesis, formal verification, and timing closure.
- Examine and recommend IP improvement, optimization and power saving enhancement.
- Perform simulation, and debug test failures at block, IP and chip level.
- Interact and support assigned block of video IP solution for various bring-up if required
- Minimum BSEE/CE, or equivalent degree.
- 8+ years of front-end design and relevant HW experience in ASIC development a MUST (outside school experience).
- Proven team leadership experience
- Strong knowledge of video codec or processing is preferred.
- Expertise in Verilog, and hands on expertise in RTL and gate level simulations.
- Expertise in synthesis, formal verification, and timing closure.
- Experience about PD design constraint is preferred, but not mandatory.
- General understanding of basic FW and essential knowledge are plus
- Strong analytical and problem solving skills along with attention to details.
- Good interpersonal skills (verbal and written).
- Must be a self starter, and able to independently lead and drive tasks to completion.
- Capable of working with team members in a global setting
Requisition Number: 62466