SMTS ASIC / Layout Design Engineer

Advanced Micro Devices   •  

Markham, ON

Industry: Semiconductors


8 - 10 years

Posted 298 days ago

This job is no longer available.

Technical engineering leader to take on the role of NBIO Silicon-Solutions-Team (SST) Lead.  The successful candidate will lead a team of system engineers to support silicon bring up, debug, validation and customer issues across all of AMD’s product segments with a focus on high speed IO IPs owned by the NBIO organization. This individual will interface with Silicon design, FW Design, Platform Design, Debug leads, Software and Validation teams to bring up and debug high priority NBIO features in silicon and provide detailed technical direction and prioritize debug actions, test planning, and execution for all aspects of NBIO IP validation from bring up to production.  The NBIO SST lead is also expected to keep NBIO and ICT senior management apprised NBIO bring up and validation progress across all AMD product platforms.

Candidate Requirements:

The candidate must have a BS or MSEE degree and a minimum of 8 years of relevant working experience in new product development from a silicon design, platform design and/or product engineering discipline. The candidate should have experience as a technical leader. The candidate must also have a strong understanding of the general silicon engineering process (preferably CPU or GPU), from concept to tape-out and then production. Furthermore the candidate should have experience with driving a multi-site and multi-disciplined engineering program teams and cross sight debug.  A successful candidate must have exceptional verbal, as well as written, communication skills.


Enterprise debug execution and leadership across AMD

  • Drive silicon debug, validation, and characterization of NBIO IPs across SOC products
  • Work with cross organization teams to ensure Silicon/SW/Platform/etc. features are in sync, development is supported, and validation is planned
  • Lead complex debug efforts for both internal and external (i.e. customer/partner) findings to identify root cause and resolution
  • Defect  prioritization and root-cause resolution plans
  • Drive solid solutions to technical issues and design challenges
  • Identify & Root-cause failures found in SoC Validation and Characterization
  • Debug OS/Application level failures using Microsoft and/or Linux Kernel Debugger.
  • Develop pre-silicon readiness and post-silicon plan to validate specific IPs/functional blocks within the SOC (covering both functional operation and electrical characteristics)
  • Collaborate with cross-functional team in developing HW/SW tools to improve SoC Validation coverage & Debug timeline
  • Work with cross-functional teams to proactively improve post-silicon Validation test strategy, methodology and process
  • Develop post-silicon validation infrastructure (Software, Hardware, Automation, and lab setup)
  • Communicate effectively with partners and customers from regions spanning the globe
  • Attend bring up and/or customer meetings
  • Provide regular updates for post silicon status
  • Perform IP unit functional testing
  • Debug any IP related open sightings reported by platform validation team and customers
  • Support IP logo certification
  • Ensures correct focus is applied to customer issues from internal and external customers, Participates in key customer communications, assist (leads) in generating errata descriptions & reports
  • Generates and presents reports (to ICT and AMD executives) of plans, progress, issues (including technical details)


  • Ability to structure and execute complex analysis, draw insights, and communicate summary findings/recommendations to senior management as well as AMD partners and customers
  • Ability to network, build relationships, and drive effective decision-making across multiple functions and levels within the organization
  • Highly organized, able to prioritize, and juggle multiple work streams to tight deadlines
  • Strong analytical skills
  • Excellent debugging skills at SoC and System level
  • Exposure to DFT Concepts (Scan, BIST), JTAG Debuggers
  • Strong knowledge of modern OS kernel (MS, Linux) and programming / scripting language (C/C++, Python, Perl, …
  • Strong understanding of industry standard IO interfaces(SATA, USB, PCIe, XGbE, IOMMU)
  • Familiarity with pre-silicon environments (Verification, Emulation, Virtual Bring-Up) is a plus
  • Prior experience with server system design and validation
  • Experience with Computer Architecture concepts and silicon features
  • Experience with Linux  and Microsoft Operating Systems, Hypervisors (VMware, KVM, XEN, Hyper-V, etc.), and validation/certification processes for each of these environments


  • Bachelor, Master's degree in Electrical or Computer engineering.

Requisition Number: 52201