Silicon Design Engineer in Santa Clara, CA

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Industry:

Telecommunications & Hardware   •  

Less than 5 years

Posted 8 weeks ago

At AMD, we push the boundaries of what is possible. We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center.

Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the "extra mile" to achieve unthinkable results. It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.

Job description

As a Timing Design engineer you will be involved with multiple phases of physical design of high performance SoC's

Your responsibilities include but are not limited to:

  • Responsible for synthesis, netlist generation, timing and logical equivalency checks, floorplanning, budgeting, clock methodology and timing constraint management.
  • Work in collaboration with RTL and Physical Design Engineers in chip level planning and integrations.
  • Generate block level static timing constraints.
  • Close timing and perform timing optimization on critical blocks by working with RTL, PD teams.
  • Generate and Implement ECOs to fix timing etc.
  • Participate in establishing CAD design methodologies.

Requirements

  • BS with 2+ years of experience /MS recent graduate
  • Some exposure to IP physical design processes, such as logical synthesis methods, and STA;
  • Proficient with industry standard frontend EDA tools;
  • Knowledge in physical design and tools.
  • Knowledge in RTL/logic design, scripting languages in Tcl/Perl; preferred experience in flow development/automation.
  • Good communication skills for interacting with logic design and physical design team members.