Serdes Architect in San Jose, CA

$100K - $150K(Ladders Estimates)

MaxLinear   •  

San Jose, CA 95101

Industry: Enterprise Technology

  •  

5 - 7 years

Posted 60 days ago

This job is no longer available.

Job Description

MaxLinear is seeking a Serdes Architect to join our San Jose, CA design center group that develops high speed wireline PHY products.

  • High-speed serdes transceiver system modeling and simulation
  • System architecture definition and tradeoff analysis, partitioning into AFE and DSP, signal processing, clock recovery, performance modeling, algorithm definition
  • Specification of jitter and noise budget, circuit/block level requirements, error correction requirements, link analysis, BER, SNR analysis
  • Work closely with circuit and digital designers to implement architecture
  • Ensure end-end performance meets specifications through mixed-mode system modeling and verification
  • Lab bring up and debug

Required Skills

  • Strong background in wireline communications
  • Knowledge of system modeling including channel characteristics, xtalk, noise, jitter, transmitter, receiver, error correction
  • Knowledge or experience in the following areas: NRZ and PAM4 modulation, signal processing, linear and feedback equalization, adaptation and calibration algorithms, high-speed signal integrity, error correction
  • Knowledge of Ethernet and PCIe standards is a plus
  • MSEE or Ph.D. with 5+ years of experience


Valid Through: 2019-9-16