Senior / Staff SoC FPGA Prototyping Engineer

Encore Semi   •  

San Jose, CA

Not Specified years

Posted 239 days ago

This job is no longer available.

Summary:

Join the growing Encore Semi Front-End Development team to collaborate with customers to design, verify and enable system level development for current and next generation ARM-based SOCs.  You would join a team delivering on many facets of the logic design of these SOCs including RTL / Microarchitecture Development, Extending Verification using Functional Coverage, Enabling Emulation Environments for intense Verification and to enable FW development and Enabling FPGA Prototyping of the design.

Essential Duties/Responsibilities/Functions/Tasks:

As a member of an ARM-based SOC development team, you will drive the creation of FPGA Prototyping models derived from the SOC RTL code and the environment to enable these models to be used to enable early Firmware development and verification of the design.  Working with the Firmware developers and the SOC Verification team, you will drive the mapping and partitioning to fit into the multiple FPGA prototyping system as well as converting structures (such as Memories and Analog blocks) in the design to models which will efficiently map to the target FPGAs.  Since the FPGA Prototypes must track the changes in the SOC design, you will develop tools, methodology and flows to efficiently track those changes to provide the latest and greatest versions to the Firmware and Verification customers.    

Minimum Qualifications:

• Experience creating and delivering FPGA Prototype platforms for SOC designs.  Experience with environments such as the Synopsys HAPS platform or other similar platforms would be very applicable.
• Experience mapping SOC designs to FPGAs most importantly partitioning internal structures to multiple FPGAs are critical.  This includes experience modeling analog blocks.
• Verilog RTL coding experience in order to specify appropriate RTL constructs which enable mapping to FPGAs or to actually recode the design to enable that mapping.
• Experience creating the various constraints (timing, I/O, etc) required to map RTL to synthesis for FPGA programming – especially for high-speed I/O blocks.
• Debug experience on physical FPGA platforms.
• Experience enabling the use of FPGA prototype systems for Firmware developers and/or Verification Engineers.
• Experience in Automation and Scripting for the creation of tools and flows for the periodic translation of RTL models into FPGA prototype programming.
• BSEE

Preferred Qualifications:

• Experience building HW Emulation models which share some similarity with building FPGA Prototype models.
• Firmware Development experience for SOCs during the “pre-silicon” phase using either Hardware Emulation or FPGA Prototyping platforms.
• SOC Verification experience using either HW Emulation, FPGA Prototype or Simulation platforms.
• MSEE