Senior Staff Signal and Power Integrity Engineer

KForce   •  

Phoenix, AZ

5 - 7 years

Posted 319 days ago

This job is no longer available.


Kforce's client, an established and growing Technology company in the Phoenix, Arizona (AZ) metro area is seeking Senior Staff Signal and Power Integrity Engineer with a strong technical background and experience in signal and power integrity. Summary: The opportunity involves working directly with our customers, design engineers, simulation engineers, business units, R&D, etc. We are looking for candidates nationwide willing to relocate to the Phoenix, AZ metro area. Once again, the position is in the Phoenix, AZ metro area. We are working directly with the Hiring Manager.

Essential Duties and Responsibilities:

  • Work with design engineers to provide design solutions for high-speed and low speed signals, clocks, power delivery signals, and power and ground planes
  • Provide routing guidelines for high-speed, low-speed, power signals, power and ground planes from bumps to balls
  • Thorough understanding of the SI and PI associated with bump signals/ground patterns and ability to optimize the balls signals/ground placement to improve the performance
  • Signal integrity analysis of frequency and time domain simulations for high speed signals and low speed signal following specifications
  • Applying a proper single ended or differential Driver and Receiver models (such as Single IBIS, IBIS_AMI, CMOS PU and PD, parallel and series terminations, ODT termination, R_ON, and Z-CAL) to optimize the driver to the associated signals
  • Optimizing single ended or differential Insertion loss, return loss, Xtlk, and power sum Xtlk for differential signaling groups and protocols
  • IR_DROP simulation for the power rails from bumps to balls
  • AC frequency sweep simulation to optimize the high RLC traces to the lower by achieving low resistance and inductance traces
  • Power plane resonance to measure the resonances of the package plans
  • PDN frequency domain and transient time domain analyses for PDN


  • Bachelor's or Master's degree in Electrical Engineering
  • At least 5-10 years of relevant experience in Signal and Power Integrity experience
  • Strong background in the application of Electromagnetics and High Speed Transmission Line principles related to signal and power integrity
  • Packaging simulation experience would be ideal
  • Proficiency in time and frequency domain modeling and use of 2D and 3D quasi-static and full-wave electromagnetic field solvers such as Cadence/Sigrity, Ansys, HFSS, or ADS
  • Experience with IC package layout tools such as Cadence APD or SiP
  • Demonstrated experience with IC package layout tools such as Cadence, Mentor or Zuken would be a plus
  • Previous experience with lab measurements such as VNA and BERT are plusses
  • Working knowledge of industry standard interfaces such as DDR, PCIe, USB, etc. are plusses
  • Prior experience with HSPICE and IBIS modeling and MATLAB and scripting experience are plusses
  • Knowledge of packaging and PCB design practices would be ideal

JobID: 1704085-WQG