Senior / Staff Analog Systems Design Engineer for Advance SerDes Architecture
As part of growing our Analog & Mixed-Signal Design team, we are hiring a Senior Analog Systems Design Engineer (RFT/full-time). You’ll be a member of a team developing advanced (sub-10ps) SerDes -- advance PHY architectures, with emphasis on high-speed receivers and signal-conditioning/equalization techniques. In this role, you will also contribute to modeling and simulations of advance analog systems, algorithm development, as well as mixed-signal system integration, bring-up and debug. A successful candidate is creative and enjoys working independently, but with an introspective critical viewpoint of conventional RF/analog designs and techniques, to contribute to team goals, and is comfortable learning new tools, methodologies and technology.
• At least 7 years of RF/high-speed analog systems experience -- 16Gbps+ designs, High-Frequency N/Frac-N PLLs, Radio Frequency Circuits, etc. is acceptable.
• Experience with analog system modeling and analysis using MATLAB; also, knowledgeable with C/C++, Python and running Debugger.
• Strong background in Communication Theory, and corresponding DSP concepts and techniques in DFE, FEC, SNR, Frequency/Time-Domain analysis (FFT, Matrix Algebra, Fixed-Point).
• In past roles, has demonstrated ability to innovate with forward looking system-level perspective.
• Knowledgeable in high-frequency design methods and measurements -- S-parameter, TDR, etc.
• Background in IBIS-AMI (also, prefer some experience with Verilog/RTL).
• Self-starter and learn new things quickly.
• Experienced with developing specifications and detail oriented.
• Excellent communication skills and can effectively report-out/present simulation/research results.
• BSEE required, MSEE preferred (or higher)