Senior / Staff Analog Mixed-Signal (AMS) Verification Engineer

5 - 7 years experience  • 

Salary depends on experience
Posted on 03/21/18
5 - 7 years experience
Salary depends on experience
Posted on 03/21/18

Job Description:

As part of growing our Analog & RF Design team, and in support of a customer partnership, we are hiring an Analog Mixed-Signal Integration and Verification Engineer.  You’ll be a member of the RFIC design & verification team focusing on the verification of mixed-signal designs at both blocks and chip-level, and working with designers to create testbenches and behavioral models to verify designs and expand that verification to cover the large number of system modes.  In this role, you will also contribute to simulations of advanced circuits, as well as mixed-signal system integration, simulations bring-up and debug.  A successful candidate is creative and enjoys working independently, operate as a self-starter, and able to work with Verilog-A, Circuits Schematics and SystemVerilog.

Required Experience & Qualification:

• BSEE/MSEE with 6+ years of experience in mixed-signal design and verification.
• Experience with Cadence AMS tools and methodologies, and able to assist with defining and driving design and verification methodologies; also able to evaluate verification methodologies and develop scripts etc. to automate verification flows.
• Understanding of RF analog sufficiently to work with analog designers to develop and validate high-performance AMS behavioral models in Verilog-A of low frequency building blocks such as LDO, Baseband filters, OpAmp, Bandgap, Charge Pump, as well as RFIC TX/RX-path building blocks (mixer, LNA, Driver Amplifier, PA, BPF, etc.)
• Experience in defining high-coverage verification plans with chip-lead and application engineers for chip-level (and blocks), and to execute and debug simulations.
• Ability to develop and bring-up AMS simulation environment: drivers, monitors, checkers and assertions. This phase requires working with both circuits and digital design teams, and also includes the creation for the electrical rule checks (ERC).
• Creating and maintaining regression test suites; preparing and holding design verification reviews and report back the failing conditions to chip-lead or application engineer; and replicate post tape-out bugs in the simulation environment and validate fixes or SW workarounds.

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