$80K - $100K(Ladders Estimates)
Job Description and Requirements
This engineer will be a member of a high-caliber R&D team creating technologies and products that enable static timing analysis and optimization of the high-speed, low-power custom digital circuits commonly used in smart-phones, tablets, CPUs, GPUs, FPGAs, etc. Specific projects include the design of circuit simulation algorithms to support analysis and optimization of complex, bleeding-edge multi-million transistor ICs and SoC chips.
Desired Skills and Experience
Valid Through: 2019-10-18