$200K — $250K *
Responsible for high performance CPU IR sign-off, and Powergrid Implementation. Perform block level IR environment setup including package, bump map setup. Work closely with PD teams to define powergrid requirements to meet sign-off criteria. Participate in world-wide PI forum and contribute to defining leading edge PI methodologies. Responsible for delivering CPM models and support successful integration at SOC level.
10+ years of hands on experience in PI of high performance CPU design with frequencies > 2 Ghz.
Experienced in hierarchical design, budgeting, multiple voltage domains and multiple clock domains.
Experience with design closure across a wide range of operating points (multi-OPP), addressing timing/IR conflicts due to congestion.
Knowledge of low-power techniques, familiarity with multi-voltage island design specification (CPF/UPF).
Strong skills with Cadence and Apache PI sign-off flows.
Strong scripting skills in tcl, perl, or python.
Experienced in working on advanced process nodes (< 16nm).
Valid through: 11/13/2021
$80K — $100K *