Senior Physical Design Lead - CSM

11 - 15 years experience  •  Business Services

Salary depends on experience
Posted on 09/22/17
Santa Clara, CA
11 - 15 years experience
Business Services
Salary depends on experience
Posted on 09/22/17

enior Physical Design Lead - CSM

  • Job Number: 33527356
  • Santa Clara Valley, California, United States
  • Posted: 13-Sep-2017
  • Weekly Hours: 40.00

Job Summary

This position is an excellent opportunity to work with a highly talented Custom Silicon team at Apple to design and develop innovative chips for the coolest products. This position focuses specifically on supporting the Physical Design and related activities for the chips.

Key Qualifications

  • Good knowledge of digital design concepts.
  • Working knowledge of front-end design methodology including basic RTL coding, synthesis methodology, timing constraints generation, multiple clock domain handling, low power techniques.
  • In depth practical, hands-on knowledge of the entire P&R methodology - including but not limited to - IO planning, ESD techniques, floor planning, power planning, clock tree synthesis, MCMM timing closure, routing, DFM techniques and physical verification.
  • Working knowledge of at least one of the industry CAD tools - Cadence, Synopsys, Mentor or Atoptech.
  • Proficient in Static Timing Analysis and the techniques used for timing closure and noise avoidance / fixing.
  • Hand-on experience in Power and Signal Integrity analysis.
  • Should have the ability to debug and fix LVS, DRC, Antenna, ERC issues.
  • Capability to work with cross-functional teams - internal and external and to handle multiple projects concurrently with very aggressive schedules.
  • Strong analytical skills with the ability to prioritize tasks and make critical decisions.
  • Willingness to travel occasionally - domestic and overseas.
  • Excellent verbal and written communication skills.
  • One or more of the following skills will be an added plus:
  • Mixed signal SoC tapeouts involving multiple instances of analog IPs.
  • Experience in DFT algorithms, memory and logic bist, physical implementation, timing closure, ATPG generation.
  • Low power / leakage management methodology and techniques.
  • Extraction and characterization of IP elements.
  • Experience of working with and managing sub-contractor design houses and silicon vendors.

Description

The successful candidate will have a BSEE / MSEE with 12+ years hands-on experience in Physical Design of SoCs. 5+ years of this should be experience in managing physical design teams. He / she should have a proven record of having taped out a number of complex chips - from gates to GDS.

Education

MSEE or BSEE required

Additional Requirements

Some travel required.

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