Senior Mixed Signal Integrated Circuits Physical Design and Tape - out Engineer
Position Summary and Responsibilities
Essential Duties of the Position:
The senior mixed-signal integrated circuits physical design and tape out engineer will work with othercircuit designers to design, physical implementation, develop, modify, and evaluate Read Out Integrated Circuits (ROIC) and their building blocks for various sub-micron technologies. The ability to understand large format ROIC physical design specification and translate them into design solutions for the specific application is an essential quality being sought for this position. The ability to work in a team environment will be a desired characteristic in this position. In this role he/she will also participate in the decision making for the design of individual sub-block, ROIC floor plan, top level integration, and tape out. General duties will include performing block level physical design, top level physical design and implementation, layout parasitic extraction, physical design verification and tape out activities.
- Strong technical background in integrated circuits physical design engineering is required
- Strong technical background in CMOS design tools such as Cadence, Calibre, and Assura
- Strong technical background in LVS, DRC, LPE, top level layout integration, and tape out activities
- Experience with analog and mixed-signal block level layout
- Advanced computer proficiency, including familiarity with Linux OS
- Experience with top level power routing, floor planning, and ESD consideration are desired
- Experience with foundry interface and tape out in large format integrated circuits physical design are desired
- Coding experience using C/C++/C#, Python, or Perl a plus
- Familiarity with maintenance of CAD tools a plus
- Strong verbal, written and presentation communication skills
- Resolves a wide range of issues in imaginative as well as practical ways
- Bachelor’s or Master’s Degree in ElectricalEngineering or related field with five (5) to fifteen (15) years of related work experience using CMOS design processes and techniques.
- Access to Teledyne’s ERP system is required; therefore, a Background Check must be passed.
- Due to the programs this position will be supporting, candidate must be a U.S. Citizen or U.S. Permanent Residents. Current security clearance or the ability to obtain a security clearance is desired.